T3.1: Analysis of current POI structure [M1-M09]

The objective of this task consists in identifying the effective limitations of the present version of standard POI stack, consisting in a 600 nm thick LiTaO3 (YXl)/42° or 50° layer, a 500 nm thick SiO2, a 1μm tick trap-rich layer onto a Si (100) substrate. This stack will be our “reference” in the next WP3 developments. In order to assess the substrate quality in a wide frequency range, UCL, INC and SOI will develop a bench of specific test structures. This will include coplanar waveguide lines of various lengths (for a wideband coverage) and various cross-sections (for wide range of E-field penetration in the substrate), cross-talk structures, inductors, SAW resonators, filters, ... This task is achieved in close cooperation with WP2, task T2.1. This test bench will be used afterwards as a test vehicle for all other alternative substrates developed in WP3/T3.2 allowing for a fair comparison between them. We will first analyse losses mechanisms and their origins via simulations and measurements in the current POI substrate. UCL will focus on the base substrate including all layers and the piezoelectric one will receive a specific attention of INC. Dominant loss paths will be identified. We will measure the insertion loss along coplanar waveguide lines, the cross-talk between metallic pads, the quality factor of inductors, resonators, etc. Effective substrate resistivity, losses in the substrate, second and third harmonic distortions will be extracted. All these analyses will be done over a frequency range (up to 130 GHz) and at various temperatures from room temperature up to 125°C. The results will feed into predictive simulations and will guide us in the development of the alternative substrates. These results will serve as a “reference point” for the benchmarking of alternative substrates developed in T3.2.