T2.1: Design of the selected filters [M04-M08]

This task is dedicated to provide a first set of filter designs answering the project requirements according to SOI expertise and database. The first step of this process consists in the definition of the POI substrate material stack to meet the main characteristics of the wave according targeted Figures of Merit (FoM). Model hypotheses concerning the overall wafer operation and more particularly the trap-rich layer are reviewed with the help of UCL to confirm the reliability of SOI design suite. Once the POI stack selected, we engage the SAW filter design process, selecting the device architectures and start design operations using SOI simulation and design tools. Comparison with requirements is achieved, yielding a so-called compliance matrix. This compliance matrix is shared with project partners, particularly TAS and ALT to select the preferred filter structures. From this design step, a first GDS file is produced and the corresponding reticule is generated. Although the main design task is the responsibility of SOI, all partners may contribute to this early design task to provide information on intrinsic dielectric and handling substrate properties of POI (UCL, INC) and on the test environment of the filter (TAS, ALT) that must be accounted for co-design purpose (acoustic simulation combined with electromagnetic analysis). At this level, UCL, INC, TAS and ALT will ask for additional patterns to be included on the reticule to characterize the above-mentioned features, for instance co-planar waveguides, circuit footprints and pad patterns, etc. This will be completed by the test structures developed in WP3, T3.1. Once all the structures fixed and defined, the reticules (there may be more than one) are ordered to complete this step. The POI wafers are ordered to SOITEC as well.